Conventional diodes have reduced a forward voltage drop VF by applying a thin wafer process and optimizing a cathode profile (e.g., see NPL 1). Wafer thinning is also effective for diodes to achieve low VF as in the case of IGBT (insulated gate bipolar transistor), which, however, leads to a reduction of the tolerance of snap-off during recovery, increasing the risk of a breakdown of the device.
Diodes targeted for a high withstand voltage class have sought to improve a recovery SOA (safe operating area) by reducing a carrier concentration in a terminal region in an ON-state by a p-layer formed on a rear side of the terminal region and suppressing carrier concentration on a boundary region during recovery (e.g., see NPL 2).
Furthermore, it has been verified also in low to medium withstand voltage classes of 600 to 1700 V that it is possible to increase electric field strength on a cathode side in addition to a main junction using p type layers and n type layers alternately formed on the rear surface side of the active region, suppress a snap-off phenomenon, and reduce total loss through the benefit of a thickness reduction of an n− type drift layer (e.g., see NPL 3).
On the other hand, in order to reduce total loss while securing a withstand voltage, if the substrate concentration is increased and the n− type drift layer is designed to have a smaller thickness, a breakdown occurs simultaneously with an avalanche in the vicinity of a breakdown starting point which substantially exceeds a rated voltage during measurement of static dielectric strength. Thus, there is a limitation on the reduction of wafer thickness for applications requiring an operation guarantee in the event of an avalanche.